In recent years, computer chip performance has bumped up against the physical limitations of the space available on integrated circuits.
Now researchers think they've found a solution: Start building upwards.
The innovation could help extend or even exceed the Moore's Law hypothesis established in the 1960s by Intel chairman Gordon Moore.
This states that through technological advancements, the number of transistors on chips should double every two years for the same cost.
More transistors generally means more processing power, but now component manufacturers are simply running out of room and ways to make transistors smaller.
The new research finds a way to stack chips vertically, using the same silicon as current technology, and with close to the same performance.
The team behind the breakthrough, from the University of Illinois Urbana-Champaign in the US, says the approach can potentially improve computing density and speed while reducing energy demands through improved efficiency and shorter connections.
"Today it takes six microelectronic devices called transistors on a single plane to store one bit of information," says materials scientist Qing Cao.
"With vertical integration, you can distribute them across multiple layers. It's like replacing a sprawling suburb with high-rises: You get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient."
Chip stacking technology has been explored before, but the big problem has been heat.
The processes required to build chips need very high temperatures, around 1,000 °C (1,832 °F) – so if you made a second layer, you're essentially going to fry the first.
While layers can be baked separately and connected afterward, or made from more heat-resistant material, this has a serious hit on processing power.
The resulting chips don't offer the same performance, layer density, or electronics integration as the 'monolithic integration' versions described here.
"Monolithic integration is what unlocks the full promise of 3D chips," Cao says.
"For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance."
The researchers got over the heat obstacle in several ways. They used what they describe as 'junctionless' transistors, essentially tweaking the chemical composition of the circuit layers so that the engineering requiring high temperatures could be done beforehand, ahead of the stacking.
They also deployed the use of ultra-thin, flexible silicon nanomembranes for their layers, rather than traditional wafers. Applying these layers is more like rolling than stacking, and can be done at temperatures less than 200 °C (392 °F).
"These membranes are mechanically flexible to conform to the underlying surface," says Cao.
"This conformality helps avoid interfacial defects like voids, which are common when trying to force two rigid wafers together via wafer bonding."
As well as using the same single-crystalline silicon as today's computer chips, the process results in high yields (very few unusable chips are produced), and the researchers are confident that it can be extended to commercially viable scales.
In these experiments, the team went up to three layers, with working logic circuits and memory cells included. That's enough to prove that the idea works, but the number of layers could be increased in the future.
There are still challenges to overcome in getting this tech out of the laboratory and into a semiconductor fabrication plant.
Right now, higher-than-normal voltages are required to power the chips, which is something that needs to be improved upon. In principle, vertical stacks should make chips more energy-efficient.
Even as advances with quantum computing continue to be made, classical computing and classical computer chips are still going to be hugely important in driving technological progress – and in fulfilling the predictions made by Gordon Moore in the 1960s.
"You can keep stacking layers beyond the three we demonstrated, and the process will yield high-performing transistors with high yield and low variability," says Cao.
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"We now have a strong foundation for transferring this technology and demonstrating its immediate promise in an industrial semiconductor foundry."
The research has been published in Nature.